This invention relates generally to semiconductor processing, and more particularly to the establishment of effective electrical interconnections through apertures extending through a dielectric layer separating two conductive layers of a semiconductor structure.
The manufacture of semiconductor devices having multiple, substantially parallel conductive layers of patterned electrical circuitry requires the effective interconnection of these layers with electrically conductive columns or vias. These vias are constructed in a variety of ways according to the prior art. In general, a via is fabricated in an aperture formed through a dielectric layer separating two electrically conductive layers. The electrically conductive layers themselves are usually metal (e.g., aluminum) in order to ensure effective conduction of electric current or, as the case may be, the storage of electric charge.
Fabrication of a multilayer, interconnected semiconductor structure typically includes the fabrication or deposition of a selected first conductive layer of a desired electrically conductive material on a prepared semiconductor substrate, such a silicon wafer provided with an insulating oxide layer. Substrates of other semiconductor materials such as gallium arsenide, and a variety of other of well-known semiconducting materials, can be used as well.
One example of a known approach for the construction of a semiconductor structure is shown in FIG. 1. The structure shown in FIG. 1 illustrates a semiconductor structure 1 including a substrate 2 such a silicon wafer W with an oxide layer 4. Deposited over the substrate 2 are first and second conductive layers 6 and 8. First conductive layer 6 is deposited on the substrate 2 over oxide layer 4. Additionally, semiconductor structure 1 includes a non-conductive layer structure 10 which is fabricated directly on first conductive layer 6 according to well known semiconductor processing techniques.
Non-conductive layer structure 10 may be constructed as a composite structure comprising multiple layers. Alternatively, layer structure 10 could comprise a single dielectric or non-conductive layer. In the case shown in FIG. 1, the composite structure of non-conductive layer structure 10 comprises three layers, respectively 12, 14, and 16. Of these, layers 12 and 16 are considered to be the outer layers and layer 14 is considered to be the inner layer. Outer layers 12 and 16 of non-conductive layer structure 10 are, for example, fabricated according to well known plasma enhanced chemical vapor deposition (PECVD) techniques, as silicon dioxide (SiO.sub.2) layers. Inner layer 14, on the other hand, is preferably created according to a spin-on-glass (SOG) technique known to those skilled in the art of semiconductor fabrication.
SOG material is problematic during and after fabrication, because of its liquid phase at the beginning of fabrication. Inner layer 14 accordingly requires curing, but it nonetheless tends to retain moisture. Even after curing operation has been completed, inner layer 14 is prone to shrinkage, cracking, and chipping, which can cause reliability problems in semiconductor structure 1. Furthermore, inner layer 14 of non-conductive layer structure 10 out-gases oxygen, nitrogen, and other gases over a considerable period of time, due to its intrinsic compound properties.
As noted, non-conductive layer structure 10 separates first and second conductive layers 6 and 8. In order to permit electrical communication between conductive layers 6 and 8, an aperture or "via hole" 18 is defined in non-conductive layer structure 10 according to well known techniques. To address the problems noted with respect to SOG in inner layer 14 of non-conductive layer structure 10, one approach of the prior art is to seal the exposed edges of inner layer 14 which were exposed by the creation of aperture 18 by means of a dielectric spacer 20, made of nitride, for example, to seal the inner surfaces of aperture 18 and to prevent out-gassing effects from SOG layer 14. Furthermore, by sealing the edges of non-conductive layer structure 10 in via aperture 18, any chipping in the structure of inner layer 14 is effectively isolated.
Unfortunately, the result of inserting dielectric spacer 20 is to reduce the effective width, "W.sub.E," of aperture 18, and therefore the actual width of via V, which serves as the electric current path from first conductive layer 6 to second conductive layer 8. This reduced width is disadvantageous, because either the electrical resistance of the via within aperture 18 is increased, or the overall design of semiconductor layer structure 10 has to be modified provide for a larger dimension aperture 18. Such a larger aperture 18 would, of course, reduce the density of devices that could be manufactured on an integrated circuit chip.